Veltra Platform

3D Heterogeneous
Multi-chip

Veltra is WHALECHIP's core 3D heterogeneous integration platform. Built on advanced bonding technologies, Veltra stacks logic, memory, and specialized dies into a single vertical package, delivering the bandwidth, density, and efficiency that next-generation AI and HPC demand.

Veltra-W · Wafer-on-Wafer

High-yield wafer-level vertical stacking via Hybrid Bonding

COMING SOON

Veltra-C · Chip-on-Wafer

Precision chiplet-level bonding for flexible high-performance integration

Veltra-W · WoW 3DIC Technology

WHALECHIP's Veltra-W is Wafer-on-Wafer (WoW) 3DIC technology within Veltra, using advanced Hybrid Bonding at the wafer level to vertically integrate chips of different types, architectures, and process nodes. Compared to typical external DDR/HBM connections in 2.5D CoWoS packaging, Veltra-W significantly increases interconnect density, eliminates PHY interface requirements, and shortens signal paths — reducing power consumption, increasing data bandwidth, and overcoming memory bottlenecks.

Architecture Evolution: 2D → 2.5D → 3D (WoW)

SoCDRAMSubstratePCB2D ArchitecturePCBSubstrateInterposerHBMStackHBM StackSoC2.5D ArchitecturePCBSubstrateLogic Die (SoC)DRAM DieHB3D Architecture (WoW)Hybrid Bonding

To meet high data flow requirements in AI / HPC applications, the 2.5D packaging approach (CoWoS) uses HBM placed around the logic chip with 1,024 pins connecting (each HBMx) to the SoC.

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SoCDRAMSubstratePCB2D ArchitecturePCBSubstrateInterposerHBMStackHBM StackSoC2.5D ArchitecturePCBSubstrateLogic Die (SoC)DRAM DieHB3D Architecture (WoW)Hybrid Bonding

Placing hundreds of chips on an interposer for 2.5D packaging is technically challenging due to space limitations.

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SoCDRAMSubstratePCB2D ArchitecturePCBSubstrateInterposerHBMStackHBM StackSoC2.5D ArchitecturePCBSubstrateLogic Die (SoC)DRAM DieHB3D Architecture (WoW)Hybrid Bonding

Whalechip WoW is true 3D stacked with 100,000+ pins, delivering over 10–100× higher bandwidth, reduced power consumption, and space-saving benefits.

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WHALECHIP WoW 3DIC 1.0

Solving the Von Neumann Bottleneck

  • Integrates logic and memory directly on two wafers via Hybrid Bonding (WoW)
  • Eliminates the Von Neumann bottleneck that has limited HPC / AI chip performance
  • 100,000+ bonding pins per chip vs 1,024 in 2.5D HBM — 100× interconnect density

Bonding Process & Package Cross-Section

DRAM WaferLogic WaferRotated &Face DownDRAM dieLogic dieHybridBondingPACKAGE CROSS-SECTIONHeat SinkThermal AdhesiveDRAM DieLogic DieHBSubstrateBGA Solder Balls

Internal Architecture — Logic Die + DRAM Die

DRAM dieMemoryMacroMemoryMacroMemoryMacroMemoryMacroMemoryMacroMemoryMacroHBLogic dieMemoryControlMemoryControlMemoryControlMemoryControlMemoryControlMemoryControlWhalechip FabricLogicCoresLogicCoresLogicCoresLogicCoresLogicCoresLogicCoresProcessingEngineManagementControlSRAM

WHALECHIP WoW 3DIC 2.0

  • WoW DRAM OIP — integrated controller, DRAM architecture & buffer die
  • 3DIC F2B / F2F — face-to-back and face-to-face hybrid bonding architectures
  • 3DIC NocSRAM — low-power cache integration for N3/N2 scaled processes
  • WeFPGA — embedded 3D switch blocks with configurable memory and logic layers

Veltra-W Platform Highlights

WoW DRAM OIPWoW DRAM ControllerWoW DRAM w/ Whalechip ArchComplete chip architecture design integrationWoW DRAM Buffer DieCompatible with TSMC process nodesDRAM CTRL SPECAXI InterfaceoutstandingInterleavingAddress remapOther FeatureMBISTRepairECCAPB for REG SettingWinbond DRAMDRAM CTRLRefreshCTRLRepairDFTSRAMAXI InterfaceAPB3DIC F2B / F2F ArchHybrid Bonding ArchitecturesFace-to-Back (F2B)Proven conventional SerDes IP,improving existing SoC reliabilityFace-to-Face (F2F)Higher bandwidth density &lower power chip-to-chip interconnectF2BWafer 1 — LogicHybrid Bond F2BWafer 2 — DRAMF2FLogic Die (face down)Hybrid Bond F2FDRAM Die (face up)3DIC NocSRAMLow-Power Cache IntegrationCOMING SOONN3/N2 process scalingPlanar L3/L4 cache cost-inefficient in 2D designsLow-power NoC SRAMImproved energy efficiency for NPU and mobileExtends standby · lower VddSRAM ZoneSOC / FPGA / NPUSubstrateWeFPGA3D eFPGA IntegrationCOMING SOON3D Switch BlocksConfigurable interconnect routing between layersConfig Memory & Logic LayersMulti-layer eFPGA programmable compute3D integration · reconfigurableWoW DRAM OIPWoW DRAM ControllerWoW DRAM w/ Whalechip ArchComplete chip architecture design integrationWoW DRAM Buffer DieCompatible with TSMC process nodesDRAM CTRL SPECAXI InterfaceoutstandingInterleavingAddress remapOther FeatureMBISTRepairECCAPB for REG SettingWinbond DRAMDRAM CTRLRefreshCTRLRepairDFTSRAMAXI InterfaceAPB3DIC F2B / F2F ArchHybrid Bonding ArchitecturesFace-to-Back (F2B)Proven conventional SerDes IP,improving existing SoC reliabilityFace-to-Face (F2F)Higher bandwidth density &lower power chip-to-chip interconnectF2BWafer 1 — LogicHybrid Bond F2BWafer 2 — DRAMF2FLogic Die (face down)Hybrid Bond F2FDRAM Die (face up)3DIC NocSRAMLow-Power Cache IntegrationCOMING SOONN3/N2 process scalingPlanar L3/L4 cache cost-inefficient in 2D designsLow-power NoC SRAMImproved energy efficiency for NPU and mobileExtends standby · lower VddSRAM ZoneSOC / FPGA / NPUSubstrateWeFPGA3D eFPGA IntegrationCOMING SOON3D Switch BlocksConfigurable interconnect routing between layersConfig Memory & Logic LayersMulti-layer eFPGA programmable compute3D integration · reconfigurableWoW DRAM OIPWoW DRAM ControllerWoW DRAM w/ Whalechip ArchComplete chip architecture design integrationWoW DRAM Buffer DieCompatible with TSMC process nodesDRAM CTRL SPECAXI InterfaceoutstandingInterleavingAddress remapOther FeatureMBISTRepairECCAPB for REG SettingWinbond DRAMDRAM CTRLRefreshCTRLRepairDFTSRAMAXI InterfaceAPB3DIC F2B / F2F ArchHybrid Bonding ArchitecturesFace-to-Back (F2B)Proven conventional SerDes IP,improving existing SoC reliabilityFace-to-Face (F2F)Higher bandwidth density &lower power chip-to-chip interconnectF2BWafer 1 — LogicHybrid Bond F2BWafer 2 — DRAMF2FLogic Die (face down)Hybrid Bond F2FDRAM Die (face up)3DIC NocSRAMLow-Power Cache IntegrationCOMING SOONN3/N2 process scalingPlanar L3/L4 cache cost-inefficient in 2D designsLow-power NoC SRAMImproved energy efficiency for NPU and mobileExtends standby · lower VddSRAM ZoneSOC / FPGA / NPUSubstrateWeFPGA3D eFPGA IntegrationCOMING SOON3D Switch BlocksConfigurable interconnect routing between layersConfig Memory & Logic LayersMulti-layer eFPGA programmable compute3D integration · reconfigurableWoW DRAM OIPWoW DRAM ControllerWoW DRAM w/ Whalechip ArchComplete chip architecture design integrationWoW DRAM Buffer DieCompatible with TSMC process nodesDRAM CTRL SPECAXI InterfaceoutstandingInterleavingAddress remapOther FeatureMBISTRepairECCAPB for REG SettingWinbond DRAMDRAM CTRLRefreshCTRLRepairDFTSRAMAXI InterfaceAPB3DIC F2B / F2F ArchHybrid Bonding ArchitecturesFace-to-Back (F2B)Proven conventional SerDes IP,improving existing SoC reliabilityFace-to-Face (F2F)Higher bandwidth density &lower power chip-to-chip interconnectF2BWafer 1 — LogicHybrid Bond F2BWafer 2 — DRAMF2FLogic Die (face down)Hybrid Bond F2FDRAM Die (face up)3DIC NocSRAMLow-Power Cache IntegrationCOMING SOONN3/N2 process scalingPlanar L3/L4 cache cost-inefficient in 2D designsLow-power NoC SRAMImproved energy efficiency for NPU and mobileExtends standby · lower VddSRAM ZoneSOC / FPGA / NPUSubstrateWeFPGA3D eFPGA IntegrationCOMING SOON3D Switch BlocksConfigurable interconnect routing between layersConfig Memory & Logic LayersMulti-layer eFPGA programmable compute3D integration · reconfigurable

Related Technical Articles

Building 3D Blocks: Different Technology Stacks

July 9, 2026

Building 3D Blocks: Different Technology Stacks

Each Whalechip technology is a different composition of the same Veltra-W building blocks. As workload scale grows, more 3DIC blocks are added — memory tiers stack higher, compute integrates deeper.

Veltra-W Platform Architecture

July 9, 2026

Veltra-W Platform Architecture

Architecture diagrams for WHALECHIP's BELUGA, ORCA, and LEVIATHAN platforms, built on Veltra-W WoW 3DIC building blocks.

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