Veltra 平台

3D 異質
多晶片整合

Veltra 是鯨鏈科技的核心 3D 異質整合平台。基於先進鍵合技術，Veltra 將邏輯、記憶體與特殊用途晶粒垂直堆疊於單一封裝中，提供下一代 AI 與 HPC 所需的頻寬、密度與效率。

Veltra-W · 晶圓對晶圓

透過混合鍵合技術實現高良率晶圓級垂直堆疊

即將推出

Veltra-C · 晶片對晶圓

精密 Chiplet 級鍵合，實現靈活的高性能整合

Veltra-W · WoW 3DIC 技術

鯨鏈科技的 Veltra-W 是 Veltra 中的晶圓對晶圓（WoW）3DIC 技術，在晶圓層級透過先進混合鍵合技術，垂直整合不同類型、架構與製程節點的晶片。相較於 2.5D CoWoS 封裝中典型的外部 DDR/HBM 連接，Veltra-W 大幅提升互連密度、省去 PHY 介面需求並縮短訊號路徑——降低功耗、提高資料頻寬、突破記憶體瓶頸。

架構演進：2D → 2.5D → 3D (WoW)

SoCDRAMSubstratePCB2D ArchitecturePCBSubstrateInterposerHBMStackHBM StackSoC2.5D ArchitecturePCBSubstrateLogic Die (SoC)DRAM DieHB3D Architecture (WoW)Hybrid Bonding

為因應 AI/HPC 應用的高資料流需求，2.5D 封裝方式（CoWoS）將 HBM 置於邏輯晶片周圍，每顆 HBMx 透過 1,024 支接腳連接至 SoC。

1
SoCDRAMSubstratePCB2D ArchitecturePCBSubstrateInterposerHBMStackHBM StackSoC2.5D ArchitecturePCBSubstrateLogic Die (SoC)DRAM DieHB3D Architecture (WoW)Hybrid Bonding

在中介層上放置數百顆晶片的 2.5D 封裝，因空間限制而面臨技術挑戰。

2
SoCDRAMSubstratePCB2D ArchitecturePCBSubstrateInterposerHBMStackHBM StackSoC2.5D ArchitecturePCBSubstrateLogic Die (SoC)DRAM DieHB3D Architecture (WoW)Hybrid Bonding

鯨鏈 WoW 採用真正的 3D 堆疊，具備超過 100,000 個鍵合接腳，提供 10–100 倍以上的更高頻寬、更低功耗與節省空間的優勢。

3

鯨鏈 WoW 3DIC 1.0

突破馮紐曼瓶頸

  • 透過混合鍵合（WoW）將邏輯與記憶體直接整合於兩片晶圓上
  • 消除限制 HPC/AI 晶片效能的馮紐曼瓶頸
  • 每顆晶片超過 100,000 個鍵合接腳，比 2.5D HBM 的 1,024 個多出 100 倍互連密度

鍵合製程與封裝截面

DRAM WaferLogic WaferRotated &Face DownDRAM dieLogic dieHybridBondingPACKAGE CROSS-SECTIONHeat SinkThermal AdhesiveDRAM DieLogic DieHBSubstrateBGA Solder Balls

內部架構——邏輯晶粒 + DRAM 晶粒

DRAM dieMemoryMacroMemoryMacroMemoryMacroMemoryMacroMemoryMacroMemoryMacroHBLogic dieMemoryControlMemoryControlMemoryControlMemoryControlMemoryControlMemoryControlWhalechip FabricLogicCoresLogicCoresLogicCoresLogicCoresLogicCoresLogicCoresProcessingEngineManagementControlSRAM

鯨鏈 WoW 3DIC 2.0

  • WoW DRAM OIP——整合控制器、DRAM 架構與緩衝晶粒
  • 3DIC F2B / F2F——面對背與面對面混合鍵合架構
  • 3DIC NocSRAM——適用於 N3/N2 先進製程的低功耗快取整合
  • WeFPGA——內嵌 3D 交換模組，具備可配置記憶體與邏輯層

Veltra-W 平台亮點

WoW DRAM OIPWoW DRAM ControllerWoW DRAM w/ Whalechip ArchComplete chip architecture design integrationWoW DRAM Buffer DieCompatible with TSMC process nodesDRAM CTRL SPECAXI InterfaceoutstandingInterleavingAddress remapOther FeatureMBISTRepairECCAPB for REG SettingWinbond DRAMDRAM CTRLRefreshCTRLRepairDFTSRAMAXI InterfaceAPB3DIC F2B / F2F ArchHybrid Bonding ArchitecturesFace-to-Back (F2B)Proven conventional SerDes IP,improving existing SoC reliabilityFace-to-Face (F2F)Higher bandwidth density &lower power chip-to-chip interconnectF2BWafer 1 — LogicHybrid Bond F2BWafer 2 — DRAMF2FLogic Die (face down)Hybrid Bond F2FDRAM Die (face up)3DIC NocSRAMLow-Power Cache Integration即將推出N3/N2 process scalingPlanar L3/L4 cache cost-inefficient in 2D designsLow-power NoC SRAMImproved energy efficiency for NPU and mobileExtends standby · lower VddSRAM ZoneSOC / FPGA / NPUSubstrateWeFPGA3D eFPGA Integration即將推出3D Switch BlocksConfigurable interconnect routing between layersConfig Memory & Logic LayersMulti-layer eFPGA programmable compute3D integration · reconfigurableWoW DRAM OIPWoW DRAM ControllerWoW DRAM w/ Whalechip ArchComplete chip architecture design integrationWoW DRAM Buffer DieCompatible with TSMC process nodesDRAM CTRL SPECAXI InterfaceoutstandingInterleavingAddress remapOther FeatureMBISTRepairECCAPB for REG SettingWinbond DRAMDRAM CTRLRefreshCTRLRepairDFTSRAMAXI InterfaceAPB3DIC F2B / F2F ArchHybrid Bonding ArchitecturesFace-to-Back (F2B)Proven conventional SerDes IP,improving existing SoC reliabilityFace-to-Face (F2F)Higher bandwidth density &lower power chip-to-chip interconnectF2BWafer 1 — LogicHybrid Bond F2BWafer 2 — DRAMF2FLogic Die (face down)Hybrid Bond F2FDRAM Die (face up)3DIC NocSRAMLow-Power Cache Integration即將推出N3/N2 process scalingPlanar L3/L4 cache cost-inefficient in 2D designsLow-power NoC SRAMImproved energy efficiency for NPU and mobileExtends standby · lower VddSRAM ZoneSOC / FPGA / NPUSubstrateWeFPGA3D eFPGA Integration即將推出3D Switch BlocksConfigurable interconnect routing between layersConfig Memory & Logic LayersMulti-layer eFPGA programmable compute3D integration · reconfigurableWoW DRAM OIPWoW DRAM ControllerWoW DRAM w/ Whalechip ArchComplete chip architecture design integrationWoW DRAM Buffer DieCompatible with TSMC process nodesDRAM CTRL SPECAXI InterfaceoutstandingInterleavingAddress remapOther FeatureMBISTRepairECCAPB for REG SettingWinbond DRAMDRAM CTRLRefreshCTRLRepairDFTSRAMAXI InterfaceAPB3DIC F2B / F2F ArchHybrid Bonding ArchitecturesFace-to-Back (F2B)Proven conventional SerDes IP,improving existing SoC reliabilityFace-to-Face (F2F)Higher bandwidth density &lower power chip-to-chip interconnectF2BWafer 1 — LogicHybrid Bond F2BWafer 2 — DRAMF2FLogic Die (face down)Hybrid Bond F2FDRAM Die (face up)3DIC NocSRAMLow-Power Cache Integration即將推出N3/N2 process scalingPlanar L3/L4 cache cost-inefficient in 2D designsLow-power NoC SRAMImproved energy efficiency for NPU and mobileExtends standby · lower VddSRAM ZoneSOC / FPGA / NPUSubstrateWeFPGA3D eFPGA Integration即將推出3D Switch BlocksConfigurable interconnect routing between layersConfig Memory & Logic LayersMulti-layer eFPGA programmable compute3D integration · reconfigurableWoW DRAM OIPWoW DRAM ControllerWoW DRAM w/ Whalechip ArchComplete chip architecture design integrationWoW DRAM Buffer DieCompatible with TSMC process nodesDRAM CTRL SPECAXI InterfaceoutstandingInterleavingAddress remapOther FeatureMBISTRepairECCAPB for REG SettingWinbond DRAMDRAM CTRLRefreshCTRLRepairDFTSRAMAXI InterfaceAPB3DIC F2B / F2F ArchHybrid Bonding ArchitecturesFace-to-Back (F2B)Proven conventional SerDes IP,improving existing SoC reliabilityFace-to-Face (F2F)Higher bandwidth density &lower power chip-to-chip interconnectF2BWafer 1 — LogicHybrid Bond F2BWafer 2 — DRAMF2FLogic Die (face down)Hybrid Bond F2FDRAM Die (face up)3DIC NocSRAMLow-Power Cache Integration即將推出N3/N2 process scalingPlanar L3/L4 cache cost-inefficient in 2D designsLow-power NoC SRAMImproved energy efficiency for NPU and mobileExtends standby · lower VddSRAM ZoneSOC / FPGA / NPUSubstrateWeFPGA3D eFPGA Integration即將推出3D Switch BlocksConfigurable interconnect routing between layersConfig Memory & Logic LayersMulti-layer eFPGA programmable compute3D integration · reconfigurable

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